This invention relates generally to integrated circuits and particularly, but not by way of limitation, to an integrated circuit memory device using insulator traps for storing charge.
Integrated circuit memory devices provide both volatile and nonvolatile storage of data. One goal in designing such devices is to increase the storage density so that more data can be stored in a memory device that occupies less volume. One technique of increasing storage density is described in a co-pending, commonly assigned U.S. patent application of L. Forbes, entitled xe2x80x9cA MULTI-STATE FLASH MEMORY CELL AND METHOD FOR PROGRAMMING SINGLE ELECTRON DIFFERENCES,xe2x80x9d Ser. No. 08/790,903, filed on Jan. 29, 1997, which disclosure is herein incorporated by reference.
The Ser. No. 08/790,903 U.S. patent application discloses a flash memory cell. The cell includes a transistor with a floating gate that is formed from a number of crystals of semiconductor material. The crystals are disposed in the gate oxide of the transistor. The size of the crystals and their distance from a surface of a semiconductor layer of the transistor are selected such that the crystals can trap a single electron by hot electron injection. Each trapped electron causes a measurable change in the drain current of the transistor. Thus, multiple data bits can be stored and retrieved by counting the changes in the drain current.
One potential shortcoming of the memory cell disclosed in the Ser. No. 08/790,903 U.S. patent application is that it does not necessarily have uniformly sized crystals. Instead, the grains have a finite grain size that may vary between individual grains. As a result, the capacitance of individual grains may also vary between individual grains. Even if such grains are capable of storing only a single electron, the resulting voltage on any particular grain may depend on the grain size. As electrons are being stored on respective grains, the resulting drain current may change in irregularly sized steps, making memory states differing only by a single stored electron difficult to distinguish. For the reasons described above, and for other reasons that will become apparent upon reading the following detailed description of the invention, there is a need for a memory cell that provides more uniformity in the step changes in drain current as single electrons are being stored on the memory cell.
The present invention provides, among other things, a memory cell that provides more uniformity in step changes in drain current as single electrons are being stored on the memory cell. In one embodiment, the invention provides a memory cell comprising an insulator carrying trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator. In another embodiment, the invention provides a memory cell comprising an insulator carrying point defect trap sites that are electrically isolated from each other by intervening portions of the insulator. In a further embodiment, the invention provides a memory cell comprising a transistor, including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate. The floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator.
Another aspect of the invention provides memory device comprising an array of memory cells. Each memory cell includes a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator. The memory device also includes addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells, and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells. Another aspect of the invention provides a computer system including the memory device as described above.
Another aspect of the invention provides a method of storing and retrieving data. The method includes altering the number of electrons stored on a memory cell in trap sites carried by an insulator at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator. A resulting parameter (e.g., current, voltage, or charge) is detected. The resulting parameter is based on the number of electrons stored in the trap sites.
In summary, the memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.